Award & Recognition:
Young Scientist Award – MPCST-Bhopal, 2012
Young Scientist Award – MPCST-Bhopal, 2013
Publication:
Book:
1. Low Power High Speed CMOS Adder, Evincepub Publishing, ISBN- 978-93-90197-10-
Patent:
1. Two Stage Operational Amplifier Using CMOS at 350NM Technology, Application No. 202011023136
2. A Modified Advanced Encryption Standard for 26 Bit Key, Application No. 202011023136
3. Speed Control of SEDM using Intelligent PI Controller, Application No. 202011021265
4. Effects of Active layer thickness on optical properties of polymer OLEDs, Application No. 202011021294
5. Visible Light Wire Less Communication, Application No. 202011022781
Refereed International Journals:
1. Raghvendra Singh “ New High Performance Low Power Carry look Ahead Adder
based on FinFET Using MTCMOS Technique” International Journal of Management, IT & Engineering Academy (IJMRA), Vol. 8Issue 9, August 2018.
2. Raghvendra Singh “ Plan and Assessment of FinFET based SRAM Cells at 22nm and 14nm Node Technologies” International Journal of Management, IT & Engineering Academy (IJMRA), Vol. 9 Issue 6, June 2019
3. Raghvendra Singh “The Impact Analysis of Channel Doping in Junction-Less Field Effect Transistor ” International Journal of Research and Analytical Reviews (IJRAR) Volume 6,Issue1, February-2019.
4. Raghvendra Singh, “ Implementation of Low Power Integrator Using Memristor ,” International Journal of Research and Analytical Reviews (E-ISSN- 2348-1269) Volume 6 issue March 2019 .
( UGC Approved)
5. Raghven dra Singh, “ New High Performance Low Power Carry look Ahead Adder based on FinFET Using MTCMOS Technique”, International Journal of Management, IT and Engineering (IJMIE), ISSN 2249-0558, Vol.8. Issue10, Published, October 2018 .( UGC Approved)
6. Raghven dra Singh, “ New High Performance 8T SRAM Cell Using FinFET Technology ”, Int ernational Journal of Management, IT and Engineering (IJMIE), ISSN 2249-0558, Vol.8. Issue9, Published, September 2018 .( UGC Approved)
7. Raghven dra Singh, “ High Speed Clock Generation for SOC with A Digital Fast Locking Pulse Width Control ”, International Journal of Electrical, Electronic, Computer Science and Engineering (IJEECSE), ISSN 2412-5156, Vol.4. Issue1, Published, March 2016.
8. Raghvendra Singh, “ Modification in 16:1 Muliplexer by Reversible Logic ”, International Journal of Engineering Science & Advanced Research (IJESAR), ISSN 2395 – 0730, Vol.2. Issue1, Published, March 2016.
9. Raghvendra Singh, “ Comparative Analysis of 28T Full Adder with 14T Full Adder using 180nm”, International Journal of Engineering Science & Advanced Research (IJESAR ) , ISSN 2395 – 0730, Vol.2. Issue 1, Published, March 2016.
10. Raghvendra Singh, “ Design and Analysis of Multi-Threshold CMOS 14T Full Adder using 180nm ”, International Journal of Engineering Science & Advanced Research (IJESAR), ISSN 2395 – 0730, Vol.2. Issue 1, Published, March 2016.
11. Raghvendra Singh, “ Analysis of Highly Stable 16-bit SRAM Array Body using Biasing Technique ”, International Journal of Engineering Science & Advanced Research (IJESAR), ISSN 2395 – 0730, Vol.1. Issue 4, Published, December 2015.
12. Raghvendra Singh, “ FinFET Based 6T-SRAM Design Using SVL Technique ”, International Journal of Engineering Science & Advanced Research (IJESAR), ISSN 2395 – 0730, Vol.1. Issue 2, Published, June 2015.
13. Raghvendra Singh, Harish Kr. Chaudhary, “ Static Noise Margin Analysis of Power SRAM Cell for High Speed Application ”, International Journal of Engineering Science & Advanced Research (IJESAR), ISSN 2395 – 0730, Vol.1. Issue 1, Published, March 2015.
14. Raghvendra Singh, Shyam Akashe, “ Design and Analysis of Low Standby Leakage Current and Reduce Ground Bounce Noise of Static CMOS 10T Full Adder ”, African Journal of Computing & ICT, Research Gate (IEEE), Published, June 2014.
15. Raghvendra Singh, Shyam Akashe, “ Modeling and Analysis of Low Power 10T Full Adder with Reduced Ground Bounce Noise”, Journal of Circuit, System, and Computer, SCOPUS Indexed (World Scientific Publisher Company), Published, January 2014.
16. Raghvendra Singh , “ Design low power SRAM using MTCMOS Technique with Nanometer Regime, International Journal of Engineering Science & Advanced Research (IJESAR ), ISSN 2395 – 0730, Vol.2. Issue4, Published, December 2016.
17. Raghvendra Singh , “ Design And Analysis Of Low power SRAM Cell Using Power gating CMOS Technology , “ International Journal of Engineering Science & Advanced Research (IJESAR), ISSN 2395 – 0730, Vol.2. Issue 3, Published, Sepetember 2016.
Refereed International Conference:
1. Raghvndra Singh, “Review Paper on Memristor,” International Conference on Engineering Science & Advance Research (ISSN No. 2395-0730) Vol.4 Issue 1, 2018.
2. Raghvendra Singh, “ FinFET Based 6T-SRAM Design Using SVL Technique”, National Conference on Trends in Signal Processing & Computing (TSPC-15), ISSN 2395 – 0730, ,Published, September 2015.
3. Raghvendra Singh, Raj Johri, Satya Prakash Panday, Shyam Akashe, “ Comparative Analysis of 10T and 14T Full Adder at 45nm Technology ,” IEEE Sponsored International Conference on Parallel Distributing and grid Computing (PDGC-2012), held at Jaypee University of Information Technology (JUIT), Waknaghat, Solan, H.P., India, 6th–8 th December 2012, Published (IEEE, Copyright).
4. Raghvendra Singh, Raj Johri, Shyam Akashe, “Modeling and Simulation of High Speed 8T SRAM cell,” Springer Sponsored International Conference on Bio-inspired Computing Theory and Application (BICTA-2012) , held at Atal Bihari Vajpayee Indian Institute of Information Technology and Management (ABV-IIITM), Gwalior, M.P., India, 14th–15th December 2012, Published ( Springer, Copyright).
5. Raghvendra Singh, Shyam Akashe, “ Modeling and Simulation of Low Power 14 T Full Adder with Reduced Ground Bounce Noise at 45nm Technology ,” IEEE Sponsored International Conference Student Conference on Engineering and System (SCES-2013), held at Motilal Nehru National Institute of Technology (MNNIT), Allahabad, U.P., India, 12th–14th April 2012, Published ( IEEE, Copyright).
6. Raghvendra Singh, Shyam Akashe, “ New High Performance Low Power 4 bit Full Adder with Reduce Ground Bounce Noise ,” IEEE Sponsored International Conference on Advanced Electronic System (ICAES-2013), held at CSIR-(CSIR-CEERI), Pilani, Raj., India, 21st–23rd, 2013, Published ( IEEE, Copyright).